R
Functional Description
CCLK
+1.2V
+1.2V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCO_2
VCCO_2
V
VCCO_2
Slave
Serial
Mode
Slave
Serial
Mode
V
‘1’
‘1’
‘1’
M2
M1
M0
‘1’
‘1’
‘1’
M2
M1
M0
Intelligent
V
Download Host
Spartan-3E
FPGA
Spartan-3E
FPGA
VCC
Configuration
CLOCK
CCLK
DIN
CCLK
DIN
Memory
Source
SERIAL_OUT
PROG_B
DONE
DOUT
DOUT
DOUT
INIT_B
INIT_B
•Internal memory
•Disk drive
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
INIT_B
TDI
TDI
•Over network
•Over RF link
GND
TMS
TCK
TMS
TCK
+2.5V
•Microcontroller
•Processor
•Tester
PROG_B
DONE
PROG_B
DONE
GND
GND
•Computer
PROG_B
PROG_B
DONE
Recommend
open-drain
driver
INIT_B
+2.5V
JTAG
TDI
TMS
TCK
TDO
TMS
TCK
DS312-2_55_082009
Figure 64: Daisy-Chaining using Slave Serial Mode
JTAG Mode
For additional information, refer to the “JTAG Configuration
Mode and Boundary-Scan” chapter in UG332.
TDI input of the next device in the chain. The TDO output of
the last device in the chain loops back to the port connector.
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the
FPGA is powered and regardless of the mode pin settings.
However, when the FPGA mode pins are set for JTAG mode
(M[2:0] = <1:0:1>), the FPGA waits to be configured via the
JTAG port after a power-on event or when PROG_B is
asserted. Selecting the JTAG mode simply disables the
other configuration modes. No other pins are required as
part of the configuration interface.
Design Note
If using software versions prior to ISE 9.1.01i, avoid config-
uring the FPGA using JTAG if...
•
•
the mode pins are set for a Master mode
the attached Master mode PROM contains a valid
FPGA configuration bitstream.
The FPGA bitstream may be corrupted and the DONE pin
may go High. The following Answer Record contains addi-
tional information.
Figure 65 illustrates a JTAG-only configuration interface.
The JTAG interface is easily cascaded to any number of
FPGAs by connecting the TDO output of one device to the
http://www.xilinx.com/support/answers/22255.htm
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
101
Product Specification