Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 78: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out Using BUFIO2
Speed Grade
Symbol
Description
Device
Units
-4
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO2
-3
-2
-1L
T
PSCS/TPHCS
IFF setup/hold using BUFIO2 clock
XC6SLX4
N/A
N/A
N/A
N/A
0.86/
0.23
1.01/
0.35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6SLX9
0.73/
0.44
0.83/
0.57
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
0.55/
0.75
0.69/
0.83
0.28/
1.12
0.28/
1.24
0.28/
1.08
0.28/
1.12
0.28/
1.24
N/A
0.44/
1.29
0.50/
1.40
0.42/
1.23
0.44/
1.29
0.50/
1.40
N/A
N/A
N/A
N/A
N/A
0.38/
1.63
0.38/
1.84
0.38/
1.53
0.38/
1.63
0.38/
1.84
N/A
0.06/
1.63
0.06/
1.87
0.06/
1.54
0.06/
1.63
0.06/
1.87
N/A
0.04/
1.75
0.04/
1.98
0.04/
1.73
0.04/
1.75
0.04/
1.98
Pin-to-Pin Clock-to-Out Using BUFIO2
TICKOFCS
OFF clock-to-out using BUFIO2 clock
XC6SLX4
N/A
N/A
N/A
N/A
5.53
N/A
5.76
N/A
5.94
N/A
6.09
N/A
6.29
5.16
5.38
5.70
6.00
6.00
6.18
6.18
6.46
6.46
6.53
6.53
6.69
6.69
6.15
6.41
6.67
7.02
7.02
7.22
7.22
7.57
7.57
7.60
7.60
7.81
7.81
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
N/A
N/A
N/A
N/A
DS162 (v1.9) August 23, 2010
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Advance Product Specification
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