Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 10: Differential I/O Standard DC Input and Output Levels
V
V
V
V
V
V
OL
ID
ICM
OD
OCM
OH
mV,
Min
mV,
mV,
V, Min V, Max mV, Min
V, Min
V, Max
V, Min
V, Max
I/O Standard
LVDS_33
Max
Max
100
100
100
200
200
100
100
100
100
150
100
100
190
600
600
–
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
2.7
0.2
0.2
0.3
0.78
0.68
0.68
0.68
0.8
0.8
0.8
1.0
1.0
1.0
1.0
0.7
0.7
0.55
2.35
2.35
2.35
1.95
1.95
2.8(1)
1.95
1.5
247
247
240
300
300
454
454
460
600
600
1.125
1.125
1.375
1.375
–
–
–
–
–
–
–
–
–
–
LVDS_25
BLVDS_25
MINI_LVDS_33
MINI_LVDS_25
LVPECL_33
LVPECL_25
RSDS_33
Typical 50% VCCO
600
600
1000
1000
–
1.0
1.0
1.4
1.4
Inputs only
Inputs only
1.4
1.4
100
100
400
100
100
–
400
400
800
400
400
–
1.0
1.0
–
–
–
–
–
–
–
–
–
–
–
–
RSDS_25
–
1.5
TMDS_33
1200
400
400
1260
–
3.23(1)
2.3
VCCO – 0.405 VCCO – 0.190
PPDS_33
0.5
0.5
1.4
1.4
PPDS_25
2.3
DISPLAY_PORT
2.35
1.02
0.9
Typical 50% VCCO
DIFF_MOBILE_DDR 100
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
90% VCCO 10% VCCO
DIFF_HSTL_I
100
100
100
100
100
100
100
100
100
100
100
100
100
–
–
–
VCCO – 0.4
CCO – 0.4
VCCO – 0.4
CCO – 0.4
VCCO – 0.4
CCO – 0.4
0.4
0.4
0.4
0.4
0.4
0.4
DIFF_HSTL_II
–
0.9
–
–
V
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL3_I
DIFF_SSTL3_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL15_II
–
0.9
–
–
–
1.1
–
–
V
–
1.1
–
–
–
1.1
–
–
V
–
1.9
–
–
V
TT + 0.6 VTT – 0.6
–
1.9
–
–
VTT + 0.8 VTT – 0.8
–
1.5
–
–
V
TT + 0.61 VTT – 0.61
–
1.5
–
–
VTT + 0.81 VTT – 0.81
–
1.1
–
–
VTT + 0.47 VTT – 0.47
–
1.1
–
–
V
TT + 0.6 VTT – 0.6
TT + 0.4 VTT – 0.4
–
0.95
–
–
V
Notes:
1. LVPECL_33 and TMDS_33 maximum V
is the lower of V (maximum) or V
– (V /2)
CCAUX ID
ICM
eFUSE Read Endurance
Table 11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For
more information, see the Spartan-6 FPGA Configuration User Guide.
Table 11: eFUSE Read Endurance
Speed Grade
Units
Symbol
Description
(Min)
-4
-3
-2
-1L
DNA_CYCLES
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
Read
Cycles
30,000,000
30,000,000
AES_CYCLES
Number of JTAG FUSE_KEY or FUSE_CNTL read command
operations. Unaffected by SHIFT operations.
Read
Cycles
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
10
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