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DS123 参数 Datasheet PDF下载

DS123图片预览
型号: DS123
PDF下载: 下载PDF文件 查看货源
内容描述: Platform Flash在系统可编程配置PROM [Platform Flash In-System Programmable Configuration PROMs]
分类和应用: 可编程只读存储器
文件页数/大小: 35 页 / 1019 K
品牌: XILINX [ XILINX, INC ]
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Platform Flash In-System Programmable Configuration PROMs  
See UG161, Platform Flash PROM User Guide, for detailed  
guidelines on PROM-to-FPGA configuration hardware  
connections, for software usage, for a reference list of Xilinx  
FPGAs, and for the respective compatible Platform Flash  
PROMs. Table 2 lists the Platform Flash PROMs and their  
capacities.  
instruction sequence. The iMPACT software also outputs  
serial vector format (SVF) files for use with any tools that  
accept SVF format, including automatic test equipment.  
During in-system programming, the CEO output is driven  
High. All other outputs are held in a high-impedance state or  
held at clamp levels during in-system programming. All  
non-JTAG input pins are ignored during in-system  
programming, including CLK, CE, CF, OE/RESET, BUSY,  
EN_EXT_SEL, and REV_SEL[1:0]. In-system programming  
is fully supported across the recommended operating  
voltage and temperature ranges.  
Table 2: Platform Flash PROM Capacity  
Platform  
Flash PROM  
Configuration  
Bits  
Platform  
Flash PROM  
Configuration  
Bits  
XCF01S  
XCF02S  
XCF04S  
1,048,576  
2,097,152  
4,194,304  
XCF08P  
XCF16P  
XCF32P  
8,388,608  
16,777,216  
33,554,432  
Embedded, in-system programming reference designs,  
such as XAPP058, Xilinx In-System Programming Using an  
Embedded Microcontroller, are available on the Xilinx web  
page for PROM Programming and Data Storage Application  
Notes. See UG161, Platform Flash PROM User Guide, for  
an advanced update methodology that uses the Design  
Revisioning feature in the Platform Flash XCFxxP PROMs.  
Programming  
The Platform Flash PROM is a reprogrammable NOR flash  
device (refer "Quality and Reliability Characteristics,"  
page 14 for the program/erase specifications).  
Reprogramming requires an erase followed by a program  
operation. A verify operation is recommended after the  
program operation to validate the correct transfer of data  
from the programmer source to the Platform Flash PROM.  
OE/RESET  
The 1/2/4 Mb XCFxxS Platform Flash PROMs in-system  
programming algorithm results in issuance of an internal  
device reset that causes OE/RESET to pulse Low.  
Several programming solutions are available.  
External Programming  
In-System Programming  
In traditional manufacturing environments, third-party  
device programmers can program Platform Flash PROMs  
with an initial memory image before the PROMs are  
assembled onto boards. Contact a preferred third-party  
programmer vendor for Platform Flash PROM support  
information. A sample list of third-party programmer  
vendors with Platform Flash PROM support is available on  
the Xilinx web page for Third-Party Programmer Device  
Support. See UG161, Platform Flash PROM User Guide,  
for the PROM data file format required for programmers.  
In-System Programmable PROMs can be programmed  
individually, or two or more can be daisy-chained together  
and programmed in-system via the standard 4-pin JTAG  
protocol as shown in Figure 3.  
X-Ref Target - Figure 3  
Pre-programmed PROMs can be assembled onto boards  
using the typical soldering process guidelines in UG112,  
Device Package User Guide. A pre-programmed PROM’s  
memory image can be updated after board assembly using  
an in-system programming solution.  
Reliability and Endurance  
(a)  
(b)  
DS123_33_031908  
Xilinx in-system programmable products provide a  
guaranteed endurance level of 20,000 in-system  
program-erase cycles and a minimum data retention of 20  
years. Each device meets all functional, performance, and  
data retention specifications within this endurance limit.  
Figure 3: JTAG In-System Programming Operation  
(a) Solder Device to PCB  
(b) Program Using Download Cable  
In-system programming offers quick and efficient design  
iterations and eliminates unnecessary package handling or  
socketing of devices. The programming data sequence is  
delivered to the device using either Xilinx iMPACT software  
and a Xilinx download cable, a third-party JTAG  
See UG116, Xilinx Device Reliability Report, for device  
quality, reliability, and process node information.  
development system, a JTAG-compatible board tester, or a  
simple microprocessor interface that emulates the JTAG  
DS123 (v2.18) May 19, 2010  
www.xilinx.com  
Product Specification  
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