R
Virtex-II Platform FPGAs: Functional Description
Sum of Products
large, flexible SOP chains. One input of each ORCY is con-
nected through the fast SOP chain to the output of the previous
ORCY in the same slice row. The second input is connected to
the output of the top MUXCY in the same slice, as shown in
Figure 25.
Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
ORCY
ORCY
ORCY
ORCY
SOP
4
4
4
4
4
4
4
4
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
MUXCY
MUXCY
MUXCY
MUXCY
Slice 1
Slice 3
Slice 1
Slice 3
MUXCY
MUXCY
MUXCY
MUXCY
4
4
4
4
4
4
4
4
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
MUXCY
MUXCY
MUXCY
MUXCY
Slice 0
Slice 2
Slice 0
Slice 2
MUXCY
V
MUXCY
V
MUXCY
V
MUXCY
V
CC
CC
CC
CC
CLB
CLB
ds031_64_110300
Figure 25: Horizontal Cascade Chain
LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions. Figure 26 illustrates
LUT and MUXCY resources configured as a 16-input AND
gate.
OUT
4
MUXCY
0
1
LUT
LUT
“0”
Slice
4
MUXCY
0
1
“0”
16
AND
OUT
4
4
MUXCY
0
1
LUT
LUT
“0”
Slice
MUXCY
0
1
V
CC
DS031_41_110600
Figure 26: Wide-Input AND Gate (16 Inputs)
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
19
XILINX [ XILINX, INC ]
