R
Virtex-II Platform FPGAs: Functional Description
Table 13: Virtex-II Logic Resources Available in All CLBs
CLB Array: Number Number
Max Distributed
SelectRAM or Shift
Register (bits)
Number
of
Flip-Flops Carry-Chains
Number
of
Number
of SOP
Chains
Row x
of
of
(1)
(1)
Device
Column
Slices
LUTs
XC2V40
8 x 8
16 x 8
256
512
8,192
16,384
512
16
16
16
XC2V80
512
1,024
1,024
32
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
112 x 104
1,536
3,072
5,120
7,680
10,752
14,336
23,040
33,792
46,592
3,072
49,152
3,072
32
48
6,144
98,304
6,144
48
64
10,240
15,360
21,504
28,672
46,080
67,584
93,184
163,840
245,760
344,064
458,752
737,280
1,081,344
1,490,944
10,240
15,360
21,504
28,672
46,080
67,584
93,184
64
80
80
96
96
112
128
160
192
224
112
144
176
208
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in Table 14.
18 Kbit Block SelectRAM Resources
Introduction
Table 14: Dual- and Single-Port Configurations
Virtex-II devices incorporate large amounts of 18 Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an 18
Kbit true dual-port RAM with two independently clocked and
independently controlled synchronous ports that access a
common storage area. Both ports are functionally identical.
CLK, EN, WE, and SSR polarities are defined through con-
figuration.
16K x 1 bit
8K x 2 bits
4K x 4 bits
2K x 9 bits
1K x 18 bits
512 x 36 bits
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18 Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
Each block SelectRAM cell is a fully synchronous memory
as illustrated in Figure 29. Input data bus and output data
bus widths are identical.
The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
DS031-2 (v3.5) November 5, 2007
Product Specification
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