R
Virtex-II Platform FPGAs: Functional Description
Locations / Organization
3-State Buffers
Four horizontal routing resources per CLB are provided for
on-chip 3-state busses. Each 3-state buffer has access
alternately to two horizontal lines, which can be partitioned
as shown in Figure 28. The switch matrices corresponding
to SelectRAM memory and multiplier or I/O blocks are
skipped.
Introduction
Each Virtex-II CLB contains two 3-state drivers (TBUFs)
that can drive on-chip busses. Each 3-state buffer has its
own 3-state control pin and its own input pin.
Each of the four slices have access to the two 3-state buff-
ers through the switch matrix, as shown in Figure 27.
TBUFs in neighboring CLBs can access slice outputs by
direct connects. The outputs of the 3-state buffers drive hor-
izontal routing resources used to implement 3-state busses.
Number of 3-State Buffers
Table 11 shows the number of 3-state buffers available in
each Virtex-II device. The number of 3-state buffers is twice
the number of CLB elements.
Table 11: Virtex-II 3-State Buffers
TBUF
3-State Buffers
per Row
Total Number
of 3-State Buffers
Device
XC2V40
TBUF
Slice
S3
16
16
128
256
Switch
Matrix
XC2V80
Slice
S2
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
32
768
Slice
S1
48
1,536
2,560
3,840
5,376
7,168
11,520
16,896
23,296
Slice
S0
64
80
DS031_37_060700
96
Figure 27: Virtex-II 3-State Buffers
112
144
176
208
The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predict-
able and less load dependant especially with larger devices.
3 - state lines
Programmable
connection
Switch
matrix
CLB-II
Switch
matrix
CLB-II
DS031_09_032700
Figure 28: 3-State Buffer Connection to Horizontal Lines
CLB/Slice Configurations
Table 12 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
implemented in one of the configurations listed. Table 13 shows the available resources in all CLBs.
Table 12: Logic Resources in One CLB
Arithmetic &
SOP
Distributed
SelectRAM
Shift
Registers TBUF
Slices
LUTs
Flip-Flops MULT_ANDs Carry-Chains Chains
4
8
8
8
2
2
128 bits
128 bits
2
DS031-2 (v3.5) November 5, 2007
Product Specification
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