R
Virtex-II Platform FPGAs: Functional Description
Figure 18, Figure 19, and Figure 20 illustrate various exam-
ple configurations.
RAM 16x1D
dual_port
RAM 16x1S
RAM
4
DPRA[3:0]
A[3:0]
G[4:1]
DPO
D
4
RAM
4
WG[4:1]
Output
D
A[3:0]
D
A[4:1]
WS
DI
4
WG[4:1]
Registered
Output
(BY)
D
Q
D
WS
DI
(BY)
WSG
(optional)
WSG
WE
CK
(SR)
WE
CK
WE
WCLK
dual_port
RAM
DS031_02_100900
4
A[3:0]
G[4:1]
SPO
D
Figure 18: Distributed SelectRAM (RAM16x1S)
WG[4:1]
WS
DI
RAM 32x1S
(BX)
WSG
A[4]
(SR)
RAM
WE
WCLK
WE
CK
4
D
A[3:0]
G[4:1]
WG[4:1]
WS DI
DS031_04_110100
(BY)
(SR)
D
Figure 20: Dual-Port Distributed SelectRAM
WSG
WE0
WE
(RAM16x1D)
Output
WE
WCLK
CK
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
Registered
Output
D Q
F5MUX
WSF
are
available:
ROM16x1,
ROM32x1,
ROM64x1,
WS
RAM
DI
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration. Table 10 shows the
number of LUTs occupied by each configuration.
(optional)
D
4
F[4:1]
WF[4:1]
Table 10: ROM Configuration
DS031_03_110100
ROM
16 x 1
32 x 1
64 x 1
128 x 1
256 x 1
Number of LUTs
Figure 19: Single-Port Distributed SelectRAM
1
(RAM32x1S)
2
4
8 (1 CLB)
16 (2 CLBs)
DS031-2 (v3.5) November 5, 2007
Product Specification
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