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DS031 参数 Datasheet PDF下载

DS031图片预览
型号: DS031
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -II FPGA平台:完整的数据表 [Virtex-II Platform FPGAs: Complete Data Sheet]
分类和应用:
文件页数/大小: 318 页 / 2407 K
品牌: XILINX [ XILINX, INC ]
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Virtex-II Platform FPGAs:  
Introduction and Overview  
DS031-1 (v3.5) November 5, 2007  
Product Specification  
Summary of Virtex-II™ Features  
Industry First Platform FPGA Solution  
IP-Immersion Architecture  
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PCI-X compatible (133 MHz and 66 MHz) at 3.3V  
PCI compliant (66 MHz and 33 MHz) at 3.3V  
CardBus compliant (33 MHz) at 3.3V  
Differential Signaling  
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Densities from 40K to 8M system gates  
420 MHz internal clock speed (Advance Data)  
840+ Mb/s I/O (Advance Data)  
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840 Mb/s Low-Voltage Differential Signaling I/O  
(LVDS) with current mode drivers  
Bus LVDS I/O  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
SelectRAM™ Memory Hierarchy  
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3 Mb of dual-port RAM in 18 Kbit block SelectRAM  
resources  
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Up to 1.5 Mb of distributed SelectRAM resources  
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Low-Voltage Positive Emitter-Coupled Logic  
High-Performance Interfaces to External Memory  
(LVPECL) I/O  
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Built-in DDR input and output registers  
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DRAM interfaces  
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SDR / DDR SDRAM  
Network FCRAM  
Reduced Latency DRAM  
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Proprietary high-performance SelectLink  
Technology  
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High-bandwidth data path  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
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SRAM interfaces  
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SDR / DDR SRAM  
QDR™ SRAM  
Supported by Xilinx Foundation™ and Alliance  
Series™ Development Systems  
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CAM interfaces  
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
Arithmetic Functions  
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Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
Flexible Logic Resources  
SRAM-Based In-System Configuration  
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Fast SelectMAP configuration  
Triple Data Encryption Standard (DES) security  
option (Bitstream Encryption)  
IEEE 1532 support  
Partial reconfiguration  
Unlimited reprogrammability  
Readback capability  
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Up to 93,184 internal registers / latches with Clock  
Enable  
Up to 93,184 look-up tables (LUTs) or cascadable  
16-bit shift registers  
Wide multiplexers and wide-input function support  
Horizontal cascade chain and sum-of-products  
support  
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Internal 3-state bussing  
0.15 µm 8-Layer Metal Process with 0.12 µm  
High-Speed Transistors  
High-Performance Clock Management Circuitry  
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Up to 12 DCM (Digital Clock Manager) modules  
1.5V (V  
) Core Power Supply, Dedicated 3.3V  
CCINT  
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Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
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Auxiliary and V  
I/O Power Supplies  
CCAUX  
CCO  
IEEE 1149.1 Compatible Boundary-Scan Logic  
Support  
Flip-Chip and Wire-Bond Ball Grid Array (BGA)  
Packages in Three Standard Fine Pitches (0.80 mm,  
1.00 mm, and 1.27 mm)  
Wire-Bond BGA Devices Available in Pb-Free  
Packaging (www.xilinx.com/pbfree)  
100% Factory Tested  
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16 global clock multiplexer buffers  
Active Interconnect Technology  
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Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of  
fanout  
SelectIO™-Ultra Technology  
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Up to 1,108 user I/Os  
19 single-ended and six differential standards  
Programmable sink current (2 mA to 24 mA) per I/O  
Digitally Controlled Impedance (DCI) I/O: on-chip  
termination resistors for single-ended I/O standards  
© 2000–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other  
trademarks are the property of their respective owners.  
DS031-1 (v3.5) November 5, 2007  
Product Specification  
www.xilinx.com  
Module 1 of 4  
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