R
Virtex-II Platform FPGAs: Pinout Information
Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
7
Pin Description
IO_L46P_7
Pin Number No Connect in XC2V1000 No Connect in XC2V1500
H2
G2
H3
H4
G3
G4
H5
H6
J6
7
IO_L46N_7
7
IO_L45P_7/VREF_7
IO_L45N_7
7
7
IO_L43P_7
7
IO_L43N_7
7
IO_L24P_7
7
IO_L24N_7
7
IO_L22P_7
7
IO_L22N_7
J7
7
IO_L21P_7/VREF_7
IO_L21N_7
K7
K8
E1
E2
D2
D3
E3
E4
F4
F5
G5
G6
H7
J8
7
7
IO_L19P_7
7
IO_L19N_7
7
IO_L06P_7
7
IO_L06N_7
7
IO_L04P_7
7
IO_L04N_7
7
IO_L03P_7/VREF_7
IO_L03N_7
7
7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
7
7
7
IO_L01N_7
0
0
0
0
0
0
1
1
1
1
1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
J12
J11
J10
F11
C6
B11
J15
J14
J13
F14
C19
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
65
XILINX [ XILINX, INC ]
