R
Virtex-II Platform FPGAs: Pinout Information
Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Pin Description
DONE
M0
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
AD22
AD4
AA5
AD5
D5
M1
M2
HSWAP_EN
TCK
E21
F5
TDI
TDO
F22
D22
AD23
F7
TMS
PWRDWN_B
DXN
DXP
C5
VBATT
RSVD
C23
C22
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
AD13
AC24
AC3
P24
N3
D24
D3
C14
W19
W8
V18
V17
V10
V9
U18
U9
K18
K9
J18
J17
J10
J9
DS031-4 (v3.5) November 5, 2007
Product Specification
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