R
Virtex-II Platform FPGAs: Pinout Information
FG676/FGG676 Fine-Pitch BGA Package
As shown in Table 8, XC2V1500, XC2V2000, and XC2V3000 Virtex-II devices are available in the FG676/FGG676 fine-pitch
BGA package. Pins in the XC2V1500, XC2V2000, and XC2V3000 devices are the same, except for the pin differences in the
XC2V1500 and XC2V2000 devices shown in the No Connect columns. Following this table are the FG676/FGG676
Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
0
Pin Description
IO_L01N_0
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
D6
C6
B1
A2
D7
C7
B3
A3
G6
G7
E6
E7
B4
A4
B5
A5
B6
A6
A7
A8
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
0
0
0
0
IO_L05N_0
0
IO_L05P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L19N_0
0
IO_L19P_0
0
IO_L21N_0
0
IO_L21P_0/VREF_0
IO_L22N_0
0
0
IO_L22P_0
0
IO_L24N_0
0
IO_L24P_0
0
IO_L25N_0
E8
D8
G8
F8
C8
B8
D9
E9
F9
G9
B9
A9
C9
NC
NC
NC
NC
NC
NC
NC
NC
0
IO_L25P_0
0
IO_L27N_0
0
IO_L27P_0/VREF_0
IO_L49N_0
0
0
IO_L49P_0
0
IO_L51N_0
0
IO_L51P_0/VREF_0
IO_L52N_0
0
0
IO_L52P_0
0
IO_L54N_0
0
IO_L54P_0
0
IO_L67N_0
DS031-4 (v3.5) November 5, 2007
Product Specification
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