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5962-9561101MZC 参数 Datasheet PDF下载

5962-9561101MZC图片预览
型号: 5962-9561101MZC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 190MHz, 320-Cell, CMOS, CQFP164, TOP BRAZED, CERAMIC, QFP-164]
分类和应用: 可编程逻辑
文件页数/大小: 76 页 / 730 K
品牌: XILINX [ XILINX, INC ]
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R
XC3000 Series Field Programmable Gate Arrays  
XC3100L CLB Switching Characteristics Guidelines  
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%  
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark  
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more  
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used  
in the simulator.  
Speed Grade  
Symbol  
-3  
-2  
Description  
Min  
Max  
Min  
Max  
Units  
Combinatorial Delay  
Logic Variables A, B, C, D, E, to outputs X or Y  
Sequential delay  
1
8
T
2.7  
2.2  
ns  
ILO  
Clock k to outputs X or Y  
Clock k to outputs X or Y when Q is returned  
through function generators F or G to drive X or Y  
T
T
2.1  
4.3  
1.7  
3.5  
ns  
ns  
CKO  
QLO  
Set-up time before clock K  
Logic Variables  
Data In  
Enable Clock  
Reset Direct Inactive  
A, B, C, D, E  
DI  
EC  
RD  
2
4
6
T
2.1  
1.4  
2.7  
1.0  
1.8  
1.3  
2.5  
1.0  
ns  
ns  
ns  
ns  
ICK  
T
DICK  
T
ECCK  
Hold Time after clock K  
Logic Variables  
Data In  
A, B, C, D, E  
DI  
EC  
3
5
7
T
0
0.9  
0.7  
0
0.9  
0.7  
ns  
ns  
ns  
CKI  
T
CKDI  
T
CKEC  
Enable Clock  
Clock  
7
Clock High time  
Clock Low time  
Max. flip-flop toggle rate  
11  
12  
T
T
1.6  
1.6  
270  
1.3  
1.3  
325  
ns  
ns  
MHz  
CH  
CL  
F
CLK  
Reset Direct (RD)  
RD width  
13  
9
T
T
2.7  
2.3  
ns  
ns  
RPW  
delay from RD to outputs X or Y  
3.1  
2.7  
RIO  
Global Reset (RESET Pad)  
RESET width (Low)  
ns  
ns  
(XC3142L)  
delay from RESET pad to outputs X or Y  
T
T
12.0  
12.0  
MRW  
12.0  
12.0  
MRQ  
Advance  
Notes: 1. The CLB K to Q delay (T  
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data  
, #5) of any CLB on the same die.  
CKO  
In hold time requirement (T  
CKDI  
2. T , T  
and T  
are specified for 4-input functions. For 5-input functions or base FGM functions, each of these  
ILO QLO  
ICK  
specifications for the XC3100L family increase by 0.35 ns (-3) and 0.29 ns (-2).  
November 9, 1998 (Version 3.1)  
7-61  
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