R
XC3000 Series Field Programmable Gate Arrays
XC3100A IOB Switching Characteristics Guidelines (continued)
I/O Block (I)
T
3
PID
I/O Pad Input
T
1
PICK
I/O Clock (IK/OK)
I/O Block (RI)
T
T
IOH
11
12
IOL
T
T
RRI
4
13
IKRI
RESET
T
OOK
T
OKO
6
5
T
RPO
15
I/O Block (O)
T
10
OP
I/O Pad Output
(Direct)
T
7
OKPO
I/O Pad Output
(Registered)
I/O Pad TS
T
9
T
TSHZ
8
TSON
I/O Pad Output
X5425
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
OUT
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
3-STATE
INVERT
T
3- STATE
(OUTPUT ENABLE)
O
D
Q
OUTPUT
BUFFER
OUT
FLIP
FLOP
I/O PAD
R
I
DIRECT IN
Q
REGISTERED IN
Q
D
FLIP
FLOP
or
TTL or
CMOS
INPUT
LATCH
THRESHOLD
R
(GLOBAL RESET)
CK1
OK
IK
CK2
PROGRAM
CONTROLLED
MULTIPLEXER
=
PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
7-58
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
