R
XC3000 Series Field Programmable Gate Arrays
XC3000 Series Pin Assignments
Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package
types, with pin counts from 44 to 208.
Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology.
Most package types are also offered with different chips to accommodate design changes without the need for PC board
changes.
Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package.
In some cases, the chip has more pads than there are pins on the package, as indicated by the information (“unused” pads)
below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specified
propagation delays and set-up times are acceptable.
In other cases, the chip has fewer pads than there are pins on the package; therefore, some package pins are not connected
(n.c.), as shown above the line in the following table.
XC3000 Series 44-Pin PLCC Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Pin No.
1
XC3030A
GND
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
XC3030A
GND
2
I/O
I/O
7
3
I/O
I/O
4
I/O
XTL2(IN)-I/O
5
I/O
RESET
6
I/O
DONE-PGM
7
PWRDWN
TCLKIN-I/O
I/O
I/O
8
XTL1(OUT)-BCLK-I/O
9
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
M1-RDATA
M0-RTRIG
M2-I/O
HDC-I/O
LDC-I/O
I/O
DIN-I/O
DOUT-I/O
CCLK
I/O
I/O
I/O
INIT-I/O
I/O
Peripheral mode and Master Parallel mode are not supported in the PC44 package
November 9, 1998 (Version 3.1)
7-65
XILINX [ XILINX, INC ]
