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5962-9561101MZC 参数 Datasheet PDF下载

5962-9561101MZC图片预览
型号: 5962-9561101MZC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 190MHz, 320-Cell, CMOS, CQFP164, TOP BRAZED, CERAMIC, QFP-164]
分类和应用: 可编程逻辑
文件页数/大小: 76 页 / 730 K
品牌: XILINX [ XILINX, INC ]
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R
XC3000 Series Field Programmable Gate Arrays  
XC3100L Switching Characteristics  
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released  
device performance parameters, please request a copy of the current test-specification revision.  
XC3100L Operating Conditions  
Symbol  
Description  
Supply voltage relative to GND Commercial 0°C to +85°C junction  
High-level input voltage  
Min  
3.0  
Max  
Units  
V
V
3.6  
CC  
V
2.0  
V
+ 0.3  
CC  
V
IH  
V
Low-level input voltage  
-0.3  
0.8  
V
IL  
T
Input signal transition time  
250  
ns  
IN  
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.  
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right  
to restrict operation to the 3.0 and 3.6 V range later, when smaller device geometries might preclude operation @ 5 V.  
Operating conditions are guaranteed in the 3.0 – 3.6 V V  
range.  
CC  
XC3100L DC Characteristics Over Operating Conditions  
Symbol  
Description  
High-level output voltage (@ I = -4.0 mA, V min)  
Min  
Max  
Units  
V
2.4  
OH  
CC  
V
OH  
High-level output voltage (@ I = -100.0 µA, V min)  
V -0.2  
CC  
V
OH  
CC  
Low-level output voltage (@ I = 4.0 mA, V min)  
0.40  
0.2  
V
OH  
CC  
V
OL  
Low-level output voltage (@ I = +100.0 µA, V min)  
V
OH  
CC  
7
V
Power-down supply voltage (PWRDWN must be Low)  
2.30  
-10  
V
CCPD  
I
Quiescent FPGA supply current  
Chip thresholds programmed as CMOS levels1  
1.5  
mA  
CCO  
I
Input Leakage Current  
+10  
µA  
IL  
Input capacitance  
(sample tested)  
C
I
IN  
All pins except XTL1 and XTL2  
XTL1 and XTL2  
Pad pull-up (when selected) @ V = 0 V 3  
10  
15  
pF  
pF  
0.02  
0.20  
0.17  
2.80  
mA  
mA  
RIN  
IN  
Horizontal long line pull-up (when selected) @ logic Low  
IRLL  
Notes: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at V  
or GND, and the FPGA  
CC  
configured with a tie option.  
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not  
exceed 100 mA per V pin. The number of ground pins varies from the XC3142L to the XC3190L.  
CC  
3. Not tested. Allows undriven pins to float High. For any other purpose, use an external pull-up.  
November 9, 1998 (Version 3.1)  
7-59  
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