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5962-9561101MZC 参数 Datasheet PDF下载

5962-9561101MZC图片预览
型号: 5962-9561101MZC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 190MHz, 320-Cell, CMOS, CQFP164, TOP BRAZED, CERAMIC, QFP-164]
分类和应用: 可编程逻辑
文件页数/大小: 76 页 / 730 K
品牌: XILINX [ XILINX, INC ]
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R
XC3000 Series Field Programmable Gate Arrays  
XC3100A CLB Switching Characteristics Guidelines  
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%  
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark  
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more  
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used  
in the simulator.  
Speed Grade  
Symbol  
-4  
-3  
-2  
-1  
-09  
Description  
Combinatorial Delay  
Min Max Min Max Min Max Min Max Min Max Units  
Logic Variables  
to outputs X or Y  
A, B, C, D, E,  
1
8
TILO  
3.3  
2.7  
2.2  
1.75  
1.5  
ns  
Sequential delay  
Clock k to outputs X or Y  
Clock k to outputs X or Y when Q is returned  
through function generators F or G to drive  
X or Y  
TCKO  
2.5  
5.2  
2.1  
4.3  
1.7  
3.5  
1.4  
3.1  
1.25  
2.7  
ns  
ns  
TQLO  
TICK  
TDICK 1.6  
TECCK 3.2  
1.0  
Set-up time before clock K  
Logic Variables  
Data In  
Enable Clock  
Reset Direct inactive RD  
A, B, C, D, E  
DI  
EC  
2
4
6
2.5  
2.1  
1.4  
2.7  
1.0  
1.8  
1.3  
2.5  
1.0  
1.7  
1.2  
2.3  
1.0  
1.5  
1.0  
2.05  
1.0  
ns  
ns  
ns  
ns  
Hold Time after clock K  
Logic Variables  
Data In  
Enable Clock  
A, B, C, D, E  
DI  
EC  
3
5
7
TCKI  
TCKDI 1.0  
TCKEC 0.8  
0
0
0.9  
0.7  
0
0.9  
0.7  
0
0.8  
0.6  
0
0.7  
0.55  
ns  
ns  
ns  
Clock  
Clock High time  
Clock Low time  
Max. flip-flop toggle rate  
11 TCH  
12 TCL  
FCLK  
2.0  
2.0  
227  
1.6  
1.6  
270  
1.3  
1.3  
323  
1.3  
1.3  
323  
1.3  
1.3  
370  
ns  
ns  
MHz  
7
Reset Direct (RD)  
RD width  
delay from RD to outputs X or Y  
Global Reset (RESET Pad)1  
RESET width (Low)  
13 TRPW 3.2  
2.7  
2.3  
2.3  
2.05  
12.0  
ns  
ns  
9
TRIO  
3.7  
3.1  
2.7  
2.4  
2.15  
12.0  
(XC3142A)  
TMRW 14.0  
TMRQ  
12.0  
12.0  
12.0  
ns  
ns  
delay from RESET pad to outputs X or Y  
14.0  
12.0  
12.0  
12.0  
Prelim  
Notes: 1. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the  
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.  
2. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these  
specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and  
0.30 ns (-09).  
November 9, 1998 (Version 3.1)  
7-55  
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