X4003/X4005
Serial Read Operations
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 9 for the address,
acknowledge, and data transfer sequences.
The read operation allows the master to access the control
register.To conform to the I2C standard, prior to issuing
the slave address byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the byte address. After acknowledging receipt of the
byte address, the master immediately issues another
start condition and the slave address byte with the R/W
bit set to one. This is followed by an acknowledge from
the device and then by the eight bit control register.
The master terminates the read operation by not
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
RESET/RESET signal is active for t
.
PURST
Figure 9. Control Register Read Sequence
S
S
S
t
o
p
t
t
a
r
Slave
Address
Byte
Address
Slave
Address
Signals from
the Master
a
r
t
t
SDA Bus
1 0 1 1 0 0 1 0
1 1 1 1 1 1 1 1
1 0 1 1 0 0 1 1
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Data Protection
Symbol Table
The following circuitry has been included to prevent
inadvertent writes:
WAVEFORM
INPUTS
OUTPUTS
– The WEL bit must be set to allow a write operation.
Must be
steady
Will be
steady
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
– A three step sequence is required before writing into
the control register to change watchdog timer or
block lock settings.
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
– The WP pin, when held HIGH, prevents all writes to
the control register.
N/A
Center Line
is High
Impedance
– Communication to the device is inhibited below the
V
voltage.
TRIP
– Command to change the control register are termi-
nated if in-progress when RESET/RESET go active.
Characteristics subject to change without notice. 9 of 18
REV 1.1.3 4/30/02
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XICOR [ XICOR INC. ]
