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X4003M8I 参数 Datasheet PDF下载

X4003M8I图片预览
型号: X4003M8I
PDF下载: 下载PDF文件 查看货源
内容描述: CPU监控器 [CPU Supervisor]
分类和应用: 光电二极管监控
文件页数/大小: 18 页 / 380 K
品牌: XICOR [ XICOR INC. ]
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X4003/X4005  
Figure 7. Acknowledge Response From Receiver  
SCL from  
Master  
1
8
9
Data Output  
from Transmitter  
Data Output  
from Receiver  
Start  
Acknowledge  
SERIAL WRITE OPERATIONS  
Slave Address Byte  
byte, the device responds with an acknowledge, and  
awaits the data. After receiving the 8 bits of the data  
byte, the device again responds with an acknowledge.  
The master then terminates the transfer by generating  
a stop condition, at which time the device begins the  
internal write cycle to the nonvolatile memory. During  
this internal write cycle, the device inputs are disabled,  
so the device will not respond to any requests from the  
master. If WP is HIGH, the control register cannot be  
changed. A write to the control register will suppress  
the acknowledge bit and no data in the control register  
will change. With WP low, a second byte written to the  
control register terminates the operation and no write  
occurs.  
Following a start condition, the master must output a  
slave address byte.This byte consists of several parts:  
– a device type identifier that is always ‘1011’.  
– two bits of ‘0’.  
– one bit of the slave command byte is a R/W bit. The  
R/W bit of the slave address byte defines the opera-  
tion to be performed.When the R/W bit is a one, then  
a read operation is selected. A zero selects a write  
operation. Refer to Figure 8.  
– After loading the entire slave address byte from the  
SDA bus, the device compares the input slave byte  
data to the proper slave byte. Upon a correct com-  
pare, the device outputs an acknowledge on the SDA  
line.  
Stops and Write Modes  
Stop conditions that terminate write operations must  
be sent by the master after sending 1 full data byte  
plus the subsequent ACK signal. If a stop is issued in  
the middle of a data byte, or before 1 full data byte plus  
its associated ACK is sent, then the device will reset  
itself without performing the write.  
Write Control Register  
To write to the control register, the device requires the  
slave address byte and a byte address. This gives the  
master access to register. After receipt of the address  
Figure 8. Write Control Register Sequence  
Byte  
Address  
Slave  
Address  
Signals from  
the Master  
Data  
SDA Bus  
1 0 1 1 0 0 1 0  
1 1 1 1 1 1 1 1  
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
Characteristics subject to change without notice. 8 of 18  
REV 1.1.3 4/30/02  
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