X28LC512/X28LC513
DEVICE OPERATION
Read
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
natesbuscontentioninasystemenvironment. Thedata
bus will be in a high impedance state when either OE or
CE is HIGH.
Write Operation Status Bits
The X28LC512/513 provides the user two write opera-
tion status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Write
Figure 1. Status Bit Assignment
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28LC512/513 supports
both a CE and WE controlled write cycle. That is, the
addressislatchedbythefallingedgeofeitherCE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.
I/O DP TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
3005 ILL F11
Page Write Operation
DATA Polling (I/O )
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The page write feature of the X28LC512/513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the X28LC512/513 prior to
the commencement of the internal programming cycle.
The host can fetch data from another device within the
systemduringapagewriteoperation(changethesource
The X28LC512/513 features DATA Polling as a method
to indicate to the host system that the byte write or page
writecyclehascompleted.DATAPollingallowsasimple
bittestoperationtodeterminethestatusoftheX28LC512/
513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
address), but the page address (A through A ) for
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complement of that data on I/O (i.e. write data = 0xxx
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each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O will reflect true data.
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The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Toggle Bit (I/O )
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The X28LC512/513 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
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XICOR [ XICOR INC. ]
