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X1228S14-4.5A 参数 Datasheet PDF下载

X1228S14-4.5A图片预览
型号: X1228S14-4.5A
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟/日历/ CPU监控器, EEPROM [Real Time Clock/Calendar/CPU Supervisor with EEPROM]
分类和应用: 外围集成电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 31 页 / 568 K
品牌: XICOR [ XICOR INC. ]
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X1228  
Table 4. Watchdog Timer Time-Out Options  
Programmable Frequency Output Bits—FO1, FO3  
These are two output control bits. They select one of  
three divisions of the internal oscillator, that is applied  
to the PHZ output pin. Table 5 shows the selection bits  
for this output. When using the PHZ output function,  
the Alarm IRQ output function is disabled.  
Watchdog Time-Out Period  
WD1 WD3  
0
0
1
1
0
1
0
1
1.75 seconds  
750 milliseconds  
250 milliseconds  
Disabled (default)  
Table 5. Programmable Frequency Output Bits  
Output Frequency  
INTERRUPT CONTROL AND FREQUENCY  
OUTPUT REGISTER (INT)  
FO1 FO3  
(average of 133 samples)  
Alarm IRQ output  
32.768kHz  
0
0
1
1
0
1
0
1
Interrupt Control and Status Bits (IM, AL1E, AL3E)  
There are two Interrupt Control bits, Alarm 1 Interrupt  
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to  
specifically enable or disable the alarm interrupt signal  
output (IRQ). The interrupts are enabled when either the  
AL1E and AL0E bits are set to ‘1’, respectively.  
4096Hz  
1Hz  
ON-CHIP OSCILLATOR COMPENSATION  
Two volatile bits (AL1 and AL0), associated with the two  
alarms respectively, indicate if an alarm has happened.  
These bits are set on an alarm condition regardless of  
whether the IRQ interrupt is enabled. The AL1 and AL0  
bits in the status register are reset by the falling edge of  
the eighth clock of a read of the register containing the  
bits.  
Digital Trimming Register (DTR) — DTR2, DTR1 and  
DTR3 (Non-Volatile)  
The digital trimming Bits DTR2, DTR1 and DTR0  
adjust the number of counts per second and average  
the ppm error to achieve better accuracy.  
DTR2 is a sign bit. DTR2=0 means frequency  
compensation is > 0. DTR2=1 means frequency  
compensation is < 0.  
Pulse Interrupt Mode  
The pulsed interrrupt mode allows for repetitive or  
recurring alarm functionality. Hence an repetitive or  
recurring alarm can be set for every nth second, or nth  
minute, or nth hour, or nth date, or for the same day of  
the week. The pulsed interrupt mode can be consid-  
ered a repetitive interrupt mode, with the repetition rate  
set by the time setting of the alarm.  
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm  
adjustment and DTR0 gives 20 ppm adjustment.  
A range from -30ppm to +30ppm can be represented  
by using three bits above.  
Table 6. Digital Trimming Registers  
The Pulse Interrupt Mode is enabled when the IM bit is  
set.  
DTR Register  
Estimated frequency  
DTR2 DTR1 DTR3  
PPM  
0 (Default)  
+10  
IM Bit  
Interrupt / Alarm Frequency  
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
Single Time Event Set By Alarm  
Repetitive / Recurring Time Event Set By  
Alarm  
1
+20  
+30  
The Alarm IRQ output will output a single pulse of  
short duration (approximately 10-40ms) once the  
alarm condition is met. If the interrupt mode bit (IM bit)  
is set, then this pulse will be periodic.  
0
-10  
-20  
-30  
Characteristics subject to change without notice. 14 of 31  
REV 1.3 3/24/04  
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