X40430/X40431 – Preliminary Information
Word Address
Data Protection
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
– RESET/RESET Signal is active for t
.
PURST
Figure 16. Sequential Read Sequence
S
t
Slave
Address
Signals from
the Master
o
A
C
K
A
C
K
A
C
K
p
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Characteristics subject to change without notice. 14 of 24
REV 1.2.3 11/28/00
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