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40430C 参数 Datasheet PDF下载

40430C图片预览
型号: 40430C
PDF下载: 下载PDF文件 查看货源
内容描述: 4k位EEPROM ,三重电压监控器,集成了CPU监控 [4kbit EEPROM, Triple Voltage Monitor with Integrated CPU Supervisor]
分类和应用: 监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 24 页 / 409 K
品牌: XICOR [ XICOR INC. ]
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X40430/X40431 – Preliminary Information  
Figure 10. Byte Write Sequence  
S
t
a
r
t
S
t
o
p
Signals from  
the Master  
Byte  
Address  
Slave  
Address  
Data  
SDA Bus  
0
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
Page Write  
This means that the master can write 16 bytes to the  
page starting at any location on that page. If the mas-  
ter begins writing at location 10, and loads 12 bytes,  
then the first 6 bytes are written to locations 10 through  
15, and the last 6 bytes are written to locations 0  
through 5. Afterwards, the address counter would point  
to location 6 of the page that was just written. If the  
master supplies more than 16 bytes of data, then new  
data overwrites the previous data, one byte at a time.  
The device is capable of a page write operation. It is  
initiated in the same manner as the byte write opera-  
tion; but instead of terminating the write cycle after the  
first data byte is transferred, the master can transmit  
an unlimited number of 8-bit bytes. After the receipt of  
each byte, the device will respond with an acknowl-  
edge, and the address is internally incremented by  
one. The page address remains constant. When the  
counter reaches the end of the page, it “rolls over” and  
goes back to ‘0’ on the same page.  
Figure 11. Page Write Operation  
(1 n 16)  
S
S
t
o
p
t
a
r
Signals from  
the Master  
Byte  
Address  
Slave  
Address  
Data  
(1)  
Data  
(n)  
t
SDA Bus  
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.  
7 Bytes  
5 Bytes  
address pointer  
ends here  
Addr = 7  
address  
10  
address  
= 6  
address  
n-1  
The master terminates the Data Byte loading by issuing  
a stop condition, which causes the device to begin the  
nonvolatile write cycle. As with the byte write operation,  
all inputs are disabled until completion of the internal  
write cycle. See Figure 11 for the address, acknowl-  
edge, and data transfer sequence.  
Characteristics subject to change without notice. 11 of 24  
REV 1.2.3 11/28/00  
www.xicor.com  
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