Production Data
WM9715L
Register 26h is for power management according to the AC’97 specification. Note that the actual state of many circuit
blocks depends on both register 24h AND register 26h.
REG
ADDR
BIT
LABEL
DEFAULT
see note
DESCRIPTION
REFER TO
14
13
12
11
10
9
PR6
PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
DAC
ADC
Disables HPOUTL, HPOUTR and OUT3 Buffer
Disables Internal Clock
Power
Management
Disables AC-link interface (external clock off)
Disables VREF, analogue mixers and outputs
Disables analogue mixers, LOUT2, ROUT2 (but not VREF)
Disables Stereo DAC and AUXDAC
8
Disables audio ADCs and input Mux
3
inverse of PR2
inverse of PR3
inverse of PR1
inverse of PR0
Read-only bit, Indicates VREF is ready
2
Read-only bit, indicates analogue mixers are ready
Read-only bit, indicates audio DACs are ready
Read-only bit, indicates audio ADCs are ready
1
0
Note: PR6 to PR0 default to 1 if the PWRUP pin is held high during reset, otherwise they default to 0.
Register 28h is a read-only register that indicates to the driver which advanced AC’97 features the WM9715L supports.
REG
ADDR
BIT
LABEL
ID
DEFAULT
DESCRIPTION
REFER TO
28h
15:14
00
Indicates that the WM9715L is configured as the primary codec in
the system.
Intel’s AC’97
Component
Specification,
Revision 2.2,
page 59
11:10
REV
01
0
Indicates that the WM9715L conforms to AC’97 Rev2.2
Indicates that the WM9715L does not support slot mapping
Indicates that the WM9715L does not have an LFE DAC
Indicates that the WM9715L does not have Surround DACs
Indicates that the WM9715L does not have a Centre DAC
9
8
7
6
3
AMAP
LDAC
SDAC
CDAC
VRM
0
0
0
0
Indicates that the WM9715L does not have a dedicated, variable
rate microphone ADC
2
1
0
SPDIF
DRA
1
0
1
Indicates that the WM9715L supports SPDIF output
Indicates that the WM9715L does not support double rate audio
Indicates that the WM9715L supports variable rate audio
VRA
Register 2Ah controls the SPDIF output and variable rate audio.
REG
ADDR
BIT
10
LABEL
SPCV
DEFAULT
1 (valid)
DESCRIPTION
SPDIF validity bit (read-only)
REFER TO
2Ah
Digital Audio
(SPDIF)
Output
5:4
SPSA
SEN
VRA
01 (slots 6, 9)
Controls SPDIF slot assignment. 00=slots 3 and 4,
01=6/9, 10=7/8, 11=10/11
2
0 (OFF)
Enables SPDIF_OUT pin (note that GC5 in register 4Ch
and GE5 in register 56h must also be set to 0)
0
0 (OFF)
Enables variable rate audio
Registers 2Ch, 2Eh 32h and control the sample rates for the stereo DAC, auxiliary DAC and audio ADC, respectively.
REG
ADDR
BIT
all
LABEL
DACSR
DEFAULT
BB80h
DESCRIPTION
REFER TO
2Ch
2Eh
32h
Controls stereo DAC sample rate
Controls auxiliary DAC sample rate
Controls audio ADC sample rate
Variable Rate
Audio /
Sample Rate
Conversion
all
all
AUXDACSR
ADCSR
BB80h
BB80h
Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz
PD Rev 4.0 December 2007
67
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
