WM9715L
Production Data
Register 1Ch controls the.recording gain.
REG
ADDR
BIT
15
LABEL
RMU
DEFAULT
1 (mute)
DESCRIPTION
Mutes audio ADC input
REFER TO
1Ch
Audio ADC,
Record Gain
14
GRL
0 (standard)
Selects gain range for PGA of left ADC. 0=0...+22.5dB in
1.5dB steps, 1=-17.25...+30dB in 0.75dB steps
13:8
7
RECVOLL
ZC
000000 (0dB)
0 (OFF)
Controls left ADC recording volume
Enables zero-cross detector
6
GRR
0 (standard)
Selects gain range for PGA of left ADC. 0=0...+22.5dB in
1.5dB steps, 1=-17.25...+30dB in 0.75dB steps
5:0
RECVOLR
000000 (0dB)
Controls right ADC recording volume
Register 20h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the
WM9715L.
REG
ADDR
BIT
13
LABEL
3DE
DEFAULT
0 (OFF)
DESCRIPTION
Enables 3D enhancement
REFER TO
20h
Audio DACs, 3D Stereo
Enhancement
7
LB
0 (OFF)
Enables loopback (i.e. feed ADC output data
directly into DAC)
Intel’s AC’97 Component
Specification, Revision 2.2, page 55
Register 22h controls 3D stereo enhancement for the audio DACs.
REG
ADDR
BIT
LABEL
3DLC
DEFAULT
0 (low)
DESCRIPTION
Selects lower cut-off frequency
REFER TO
22h
5
4
Audio DACs,
3D Stereo
Enhancement
3DUC
0 (high)
Selects upper cut-off frequency
Controls depth of 3D effect
3:0
3DDEPTH
0000 (0%)
Register 24h is for power management additional to the AC’97 specification. Note that the actual state of each circuit block
depends on both register 24h AND register 26h.
REG
ADDR
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Power
24h
15
14
13
12
11
10
9
PD15
PD14
PD13
PD12
PD11
PD10
PD9
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
0 *
Disables Crystal Oscillator
Disables left audio DAC
Disables right audio DAC
Disables left audio ADC
Disables right audio ADC
Disables MICBIAS
Management
Disables left headphone mixer
8
PD8
Disables right headphone mixer
7
PD7
Disables speaker mixer
6
PD6
Disables MONO_OUT buffer (pin 33) and phone mixer
Disables OUT3 buffer (pin 37)
5
PD5
4
PD4
Disables headphone buffers (HPOUTL/R)
Disables speaker outputs (LOUT2, ROUT2)
Disables Line Input PGA (left and right)
Disables Phone Input PGA
3
PD3
2
PD2
1
PD1
0
PD0
Disables Mic Input PGA (left and right)
* “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0.
PD Rev 4.0 December 2007
66
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
