Pre-Production
WM8985
REGISTER
ADDRESS
BIT
LABEL
VROI
DEFAULT
DESCRIPTION
R49 (31h)
0
0
VREF (AVDD1/2) to analogue output
resistance
0 = approx 1kΩ
1 = approx 30 kΩ
Table 41 Disabled Outputs to VREF Resistance
A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 30. This
buffer can be enabled using the BUFIOEN register bit.
Figure 30 summarises the bias options for the output pins.
Analogue inputs
1k
LOUT1
30k
VROI
R49[0]
1k
ROUT1
30k
VROI
R49[0]
-
AVDD/2
AVDD/2
+
BUFIOEN
R1[2]
1k
OUT4
OUT3
Used to tie off all unused
inputs and outputs
30k
VROI
R49[0]
1k
30k
VROI
R49[0]
1k
LOUT2
ROUT2
30k
VROI
R49[0]
1k
30k
VROI
R49[0]
Figure 30 Unused Input/Output Pin Tie-off Buffers
L/ROUT2EN/
VROI
OUTPUT CONFIGURATION
OUT3/4EN
0
0
1
0
1
X
1kΩ to AVDD1/2
30kΩ to AVDD1/2
Output enabled (DC level=AVDD1/2)
Table 42 Unused Output Pin Bias Options
PP, Rev 3.4, October 2006
73
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
