Pre-Production
WM8985
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Left output volume:
R54 (36h)
5:0
LOUT2VOL
111001
LOUT2
Volume
control
(1dB steps)
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
Left output mute:
0 = Normal operation
1 = Mute
6
7
LOUT2MUTE
LOUT2ZC
0
0
LOUT2 volume zero cross enable:
1 = Change gain on zero cross only
0 = Change gain immediately
8
OUT2VU
Not latched LOUT2 and ROUT2 volumes do not
update until a 1 is written to SPKVU
(in reg 54 or 55)
R55 (37h)
5:0
ROUT2VOL
111001
Right output volume:
(1dB steps)
ROUT2
Volume
control
000000 = -57dB
...
111001 = 0dB
...
111111 = +6dB
6
7
8
ROUT2MUTE
ROUT2ZC
OUT2VU
0
0
Right output mute:
0 = Normal operation
1 = Mute
ROUT2 volume zero cross enable:
1 = Change gain on zero cross only
0 = Change gain immediately
Not latched LOUT2 and ROUT2 volumes do not
update until a 1 is written to SPKVU
(in reg 54 or 55)
Table 36 OUT2 Volume Control
ZERO CROSS TIMEOUT
A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs
the gain will automatically update after a timeout period if a zero cross has not occurred. This is
enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital
and is equal to 221 * SYSCLK period.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
0
SLOWCLKEN
0
Slow clock enable
Additional
Control
0 = slow clock disabled
1 = slow clock enabled
Table 37 Timeout Clock Enable Control
Note: SLOWCLKEN is also used for the jack insert detect debounce circuit
PP, Rev 3.4, October 2006
69
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
