Pre-Production
WM8985
Figure 32 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The
other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency
and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of
the next.
Figure 33 I2S Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the LRC pulse shown in Figure 34 and Figure
35. In device slave mode, Figure 36 and Figure 37, it is possible to use any length of LRC pulse less
than 1/fs, providing the falling edge of the LRC pulse occurs greater than one BCLK period before the
rising edge of the next LRC pulse.
Figure 34 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
PP, Rev 3.4, October 2006
75
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
