WM8961
Pre-Production
MASTER MODE BCLK AND LRC GENERATION
The BCLK frequency is controlled by BCLKDIV[3:0] which must be set appropriately to support the
ADC and DAC sample rate.
The LRC is set by the LRCLK_RATE[ 8:0] which is an integer division of the BCLK.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
BCLK Frequency (Master Mode)
R8 (08h)
3:0
BCLKDIV[3:0]
0100
0000 = SYSCLK
Clocking2
0001 = Reserved
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4 (default)
0101 = Reserved
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = Reserved
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 24
1100 = Reserved
1101 to 1111 = SYSCLK / 32
Integer divide of BCLK. 50:50 LRCLK duty cycle is only
guaranteed with even values (4, 6, … … , 510).
R14 (0Eh) Audio
Interface 2
8:0
LRCLK_RATE[8:0] 0_0100_0000
0_0000_0000 to 0_0000_0011 : reserved
0_0000_0100 : 4
…
0_0100_0000 : 64
…
1_1111_1110 : 510
1_1111_1111: Reserved
Table 43 Master Mode BCLK and LRC Configuration
Internal clock divide and phase control mechanisms ensure that the BCLK and LRC edges will occur
in a predictable and repeatable position relative to each other and to the data.
See Clocking and Sample Rates section for more information.
PP, August 2009, Rev 3.1
w
59
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
