WM8961
Pre-Production
In DSP mode, the left channel MSB is available on either the 1st (DSP mode B) or 2nd (DSP mode A)
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 34 and Figure
35. In device slave mode, Figure 36 and Figure 37, it is possible to use any length of frame pulse less
than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before
the rising edge of the next frame pulse.
Figure 34 DSP Mode Audio Interface (mode A, LRP=0, Master)
Figure 35 DSP Mode Audio Interface (mode B, LRP=1, Master)
Figure 36 DSP Mode Audio Interface (mode A, LRP=0, Slave)
PP, August 2009, Rev 3.1
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61
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
