WM8961
Pre-Production
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data into the WM8961 and outputting ADC data
from it. It uses four pins:
•
•
•
•
ADCDAT: ADC data output
DACDAT: DAC data input
LRC: DAC and ADC data alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK and LRC can be an output when the WM8961 operates as a master, or an
input when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
•
•
•
•
Left justified
Right justified
I2S
DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE OPERATION
The WM8961 can be configured as either a master or slave mode device. As a master device the
WM8961 generates BCLK and LRC and thus controls sequencing of the data transfer on ADCDAT
and DACDAT. In slave mode, the WM8961 responds with data to clocks it receives over the digital
audio interface. Master and slave modes are illustrated below.
Figure 29 Master Mode
Figure 30 Slave Mode
PP, August 2009, Rev 3.1
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
