WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Secondary HPL PGA Volume
R71 (47h)
8:6
HPL_VOL[2:0]
111
Analogue HP 2
111
110
101
100
011
010
001
000
0dB (default)
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
5:3
HPR_VOL[2:0]
111
Secondary HPR PGA Volume
111
110
101
100
011
010
001
000
0dB (default)
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
Table 29 Headphone Output Drive Volume Control
HEADPHONE OUTPUT ENABLE
The staged enabling of the headphone outputs can be controlled using register R69. The HPL_ENA
and HPR_ENA enable the headphone amplifiers. The HPL_ENA_OUTP and HPR_ENA_OUTP
should be enabled following any offset cancellation by the DC Servo.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Left channel output short removal: set after output stage
has been enabled
R69 (45h)
Analogue
HP 0
7
6
5
HPL_RMV_SHORT
HPL_ENA_OUTP
HPL_ENA_DLY
0
0
0
Enables left channel output stage; set after offset
cancellation is done
delayed left channel enable, set with at least 20us delay
to HPL_ENA; reset together with HPL_ENA
Enables left headphone amplifier channel
4
3
HPL_ENA
0
0
right channel output short removal: set after output
stage has been enabled
HPR_RMV_SHORT
enables right channel output stage; set after offset
cancellation is done
2
1
0
HPR_ENA_OUTP
HPR_ENA_DLY
HPR_ENA
0
0
0
delayed right channel enable, set with at least 20us
delay to HPR_ENA; reset together with HPR_ENA
Enables right headphone amplifier channel
Table 30 Headphone Output Enable Control
HEADPHONE OUTPUT CIRCUIT
It is recommended that the HP-L and HP_R is connected to a zobel network consisting of a 20ꢀ
resistor (5% tolerance) and a 100nF capacitor (20% tolerance). This ensures the stability of the
headphone output amplifier. This is also illustrated in Figure 19.
PP, August 2009, Rev 3.1
w
44
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
