WM8961
Pre-Production
Note that the register write to CP_DYN_PWR[1:0] must take place before the charge pump is
enabled. See the “Charge Pump” section.
SPEAKER OUTPUTS
The SPK_LP/SPK_LN and SPK_RP/SPK_RN output pins are class D speaker drivers. Each pair is
independently controlled and can drive an 8Ω BTL speaker. Output PGA volume is relative to AVDD,
while an additional boost stage (set by CLASSD_ACGAIN[2:0] ) is available to accommodate higher
SPKVDD1/SPKVDD2 supply voltages. This allows AVDD to be run at a lower voltage to save power,
while maximum output power can be delivered to the load, utilising the full range of SPKVDD1 and
SPKVDD2 supplies. The output gain stage automatically centers the analogue output about
SPKVDD/2. This will avoid the analogue output clipping
–
except in the case of
CLASSD_ACGAIN=12dB. The speaker output stage is illustrated in Figure 20
Figure 20 Speaker Output Stage
PP, August 2009, Rev 3.1
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
