WM8961
Pre-Production
ADCL_DAC_SVOL or
SIDETONE
ADCR_DAC_SVOL
0000
VOLUME
-36
-33
-30
-27
-24
-21
-18
-15
-12
-9
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
-6
1011
-3
1100
0
1101
0
1110
0
1111
0
Table 26 Digital Sidetone Volume in dB
DAC OVERSAMPLING
In order to increase the signal to noise ratio (SNR) of the DAC output, the DAC_OSR128 register bit
can be used to increase the oversampling rate of the DAC as shown in Table 31. The
MANUAL_MODE register bit is detailed in “ADC and DAC Clocking and Sample Rates”. There will be
a slight increase in power consumption when 128OSR mode is selected.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R6 (06h)
ADC & DAC
Control 2
0
DAC_OSR128
0
DAC 128 Over Sampling Rate
0: 64x DAC oversampling
1: If MANUAL_MODE=0, automatically
configure DACDIV[2:0] for 128OSR
mode. This will give a SNR
improvement at the expense of power
Table 27 DAC Oversampling Control
ANALOGUE OUTPUTS
WM8961 has 2 analogue output paths. One path drives a ground referenced headphone output which
is powered by a charge pump. In this path, a DC servo is used to remove any offsets from the
headphone outputs. The second path drives the Class D speaker outputs.
HEADPHONE OUTPUTS
The headphone output consists of 2 stages, a Volume PGA, followed by an output drive stage
containing an integrated PGA, as illustrated in Figure 18. The headphone output stage must be
enabled during normal operation, which permits power saving when not in use. The headphone bias
current can be controlled to improve SNR. For details of the DC Servo, refer to the “DC Servo”
section.
PP, August 2009, Rev 3.1
w
41
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
