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WM8945 参数 Datasheet PDF下载

WM8945图片预览
型号: WM8945
PDF下载: 下载PDF文件 查看货源
内容描述: 单声道低功耗编解码器与视频缓冲器和触摸屏控制器 [Mono Low-Power CODEC with Video Buffer and Touch Panel Controller]
分类和应用: 解码器编解码器控制器
文件页数/大小: 169 页 / 1604 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8945  
Production Data  
Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent  
signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be  
prevented by reducing the analogue signal gain or by adjusting the source signal.  
The Anti-Clip and Quick Release features should not be used at the same time.  
QUICK-RELEASE CONTROL  
The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the  
intended source signal. For example, in handheld microphone recording, transient signal peaks  
sometimes occur due to user handling, key presses or accidental tapping against the microphone.  
The Quick Release feature ensures that these transients do not cause the intended signal to be  
masked by the longer time constants of DRC_DCY.  
The Quick-Release feature is enabled by setting the DRC_QR bit. When this bit is enabled, the DRC  
measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a  
transient peak that may not be related to the intended source signal. If the crest factor exceeds the  
level set by DRC_QR_THR, then the normal decay rate (DRC_DCY) is ignored and a faster decay  
rate (DRC_QR_DCY) is used instead.  
The DRC Quick-Release control bits are described in Table 22.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DRC_QR  
DEFAULT  
DESCRIPTION  
R29 (1Dh)  
DRC Quick-release Enable  
0 = Disabled  
2
1
DRC Control 1  
1 = Enabled  
R34 (22h)  
DRC_QR_THR  
[1:0]  
DRC Quick-release threshold (crest  
factor in dB)  
3:2  
1:0  
00  
00  
DRC Control 6  
00 = 12dB  
01 = 18dB  
10 = 24dB  
11 = 30dB  
DRC_QR_DCY  
[1:0]  
DRC Quick-release decay rate  
(seconds/6dB)  
00 = 0.725ms  
01 = 1.45ms  
10 = 5.8ms  
11 = reserved  
Table 22 DRC Quick-Release Control  
The Anti-Clip and Quick Release features should not be used at the same time.  
DRC INITIAL VALUE  
The DRC can be set up to a defined initial condition based on the expected signal level when the  
DRC is enabled. This can be set using the DRC_INIT bits in register R35 (23h) bits 4 to 0.  
Note: This does NOT set the initial gain of the DRC. It sets the expected signal level of the DRC input  
signal when the DRC is enabled.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DRC_INIT  
DEFAULT  
DESCRIPTION  
R35 (23h)  
Initial value at DRC startup  
00000 = 0dB  
4:0  
00000  
DRC Control 7  
00001 = -3.75dB  
… (-3.75dB steps)  
11111 = -116.25dB  
PD, May 2011, Rev 4.1  
44  
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