WM8945
Production Data
The digital microphone interface control fields are described in Table 6.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
DMIC_ENA
Enables Digital Microphone mode
0 = Audio DSP input is from ADC
7
0
Power
Management 1
1 = Audio DSP input is from digital
microphone interface
When DMIC_ENA = 0, the Digital
microphone clock (DMICCLK) is
held low.
Table 6 Digital Microphone Interface Control
ANALOGUE-TO-DIGITAL CONVERTER (ADC)
The WM8945 uses a 24-bit sigma-delta ADC. The use of multi-bit feedback and high oversampling
rates reduces the effects of jitter and high frequency noise. The ADC full-scale input level is
proportional to LDOVOUT. See “Electrical Characteristics” section for further details. Any input signal
greater than full scale may overload the ADC and cause distortion.
The ADCs and associated digital record filters are enabled by the ADCL_ENA register bit.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
ADCL_ENA
0
Left ADC Enable
10
Power
Management
1
0 = Disabled
1 = Enabled
ADCL_ENA must be set to 1 when
processing left channel data from
the ADC or Digital Microphone.
Table 7 ADC Enable Control
ADC VOLUME CONTROL
The output of the ADC can be digitally amplified or attenuated over a range from -71.625dB to
+23.625dB in 0.375dB steps. The volume of each channel is controlled using ADCL_VOL. The ADC
Volume is part of the ADC Digital Filters block. The gain for a given eight-bit code X is given by:
0.375 (X-192) dB for 1 X 255;
MUTE for X = 0
The ADC_VU bit controls the loading of digital volume control data. The ADCL_VOL control data is
only loaded into the respective control register when ADC_VU = 1.
The output of the ADC can be digitally muted using the ADCL_MUTE or ADC_MUTEALL bits.
PD, May 2011, Rev 4.1
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