WM8941
Pre Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
26 (1Ah)
27 (1Bh)
28 (1Ch)
29 (1Dh)
30 (1Eh)
31(1Fh)
32 (20h)
15:0
15:0
15:0
15:0
15:0
15:0
0000h
0000h
0000h
0000h
0000h
0000h
000000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
15:10 ALCGAIN[5:0]
Readback from this register will return the ALC gain in Input Limiter /
this position
Automatic Level
Control (ALC)
9
0
0
Reserved
8
ALCSEL
ALC function select
0=ALC disabled
1=ALC enabled
Reserved
Input Limiter /
Automatic Level
Control (ALC)
7:6
5:3
00
ALCMAX
ALCMIN
111
Set Maximum Gain of PGA
Input Limiter /
Automatic Level
Control (ALC)
2:0
000
Set minimum gain of PGA
Input Limiter /
Automatic Level
Control (ALC)
33 (21h)
15:8
7:4
000h
000
Reserved
ALCHLD
ALCLVL
ALC hold time before gain is increased.
Input Limiter /
Automatic Level
Control (ALC)
3:0
1011
ALC threshold level. Sets the desired signal level.
Input Limiter /
Automatic Level
Control (ALC)
34 (22h)
15:9
8
00h
0
Reserved
ALCMODE
Determines the ALC mode of operation:
0=Normal mode
Input Limiter /
Automatic Level
Control (ALC)
1=Limiter mode.
7:4
3:0
ALCDCY
ALCATK
0011
0010
Decay (gain ramp-up) time
Input Limiter /
Automatic Level
Control (ALC)
ALC attack (gain ramp-down) time
Input Limiter /
Automatic Level
Control (ALC)
35 (23h)
15:4
3
000h
0
Reserved
NGEN
NGTH
Noise gate function enable
1 = enable
Input Limiter /
Automatic Level
Control (ALC)
0 = disable
2:0
000
Noise gate threshold
Input Limiter /
Automatic Level
Control (ALC)
36 (24h)
15:8
7
00h
0
Reserved
PLL_POWERD
OWN
PLL POWER
0=On
Master Clock and
Phase Locked
Loop (PLL)
1=Off
6
FRACEN
1
Fractional Divide within the PLL
0=Disabled (Lower Power)
1=Enabled
Master Clock and
Phase Locked
Loop (PLL)
5:4
PLLPRESCALE 00
00 = MCLK input multiplied by 2 (default)
01 = MCLK input not divided
10 = Divide MCLK by 2 before input to PLL
11 = Divide MCLK by 4 before input to PLL
Master Clock and
Phase Locked
Loop (PLL)
PP, Rev 3.3, December 2007
84
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
