WM8941
Pre Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0
MICP2INPPGA
0
Connect input PGA amplifier positive terminal to MICP Input Signal Path
or VMID.
0 = input PGA amplifier positive terminal connected to
VMID
1 = input PGA amplifier positive terminal connected to
MICP through variable resistor string
45 (2Dh)
15:8
7
00h
0
Reserved
INPPGAZC
Input PGA zero cross enable:
Input Signal Path
Input Signal Path
Input Signal Path
0=Update gain when gain register changes
1=Update gain on 1st zero cross after gain register
write.
6
INPPGAMUTE
INPPGAVOL
1
Mute control for input PGA:
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected from the
following input BOOST stage).
5:0
010000
Input PGA volume
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = 35.25dB
Reserved
46 (2Eh)
47 (2Fh)
15:0
15:9
8
0000h
00h
0
Reserved
PGABOOST
Input Boost
Input Signal Path
Input Signal Path
0 = PGA output has +0dB gain through input BOOST
stage.
1 = PGA output has +20dB gain through input BOOST
stage.
7
0
Reserved
6:4
MICP2BOOSTVOL 000
Controls the MICP pin to the input boost stage (NB,
when using this path set MICP2INPPGA=0):
000=Path disabled (disconnected)
001=-12dB gain through boost stage
010=-9dB gain through boost stage
…
111=+6dB gain through boost stage
Reserved
3
0
2:0
AUX2BOOSTVOL 000
Controls the auxiliary amplifier to the input boost
stage:
Input Signal Path
000=Path disabled (disconnected)
001=-12dB gain through boost stage
010=-9dB gain through boost stage
…
111=+6dB gain through boost stage
Reserved
48 (30h)
49 (31h)
15:0
15:2
1
0000h
0000h
1
Reserved
TSDEN
VROI
Thermal Shutdown Enable
0 : thermal shutdown disabled
1 : thermal shutdown enabled
Output Switch
0
0
VREF (AVDD/2 or 1.5xAVDD/2) to analogue output
resistance
Analogue Outputs
0: approx 1kΩ
1: approx 30 kΩ
Reserved
50 (32h)
15:6
000h
PP, Rev 3.3, December 2007
86
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
