WM8941
Pre Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0
MS
0
Sets the chip to be master over FRAME and BCLK
0=BCLK and FRAME clock are inputs
Digital Audio
Interfaces
1=BCLK and FRAME clock are outputs generated by
the WM8941 (MASTER)
7 (07h)
15:7
6
00000
0
Reserved
POB_CTRL
SOFT_START
TOGGLE
SR
Power on Bias Control
0=normal (current bias based on VMID)
1=Startup (current bias not based on VMID)
VMID Soft Start
POP Minimisation
POP Minimisation
POP Minimisation
5
0
0=disabled
1=enabled
4
0
Fast VMID Discharge
0=normal
1=enable (used during power-down)
3:1
000
Approximate sample rate (configures the coefficients
for the internal digital filters):
Audio Sample
Rates
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
0
SLOWCLKEN
MODE_GPIO
0
Enables the Timeout Clock for zero cross detection.
Zero Cross
Timeout
8 (08h)
15:8
7
00h
0
Reserved
Selects MODE as a GPIO pin
Control Interface
0 = MODE is an input. MODE selects 2-wire mode
when low and 3-wire mode when high.
1 = MODE can be an input or output under the control
of the GPIO control register. Interface operates in 3-
wire mode regardless of when happens on the MODE
pin.
6
0
Reserved
5:4
OPCLKDIV
00
PLL Output clock division ratio
00=divide by 1
General Purpose
Input Output
01=divide by 2
10=divide by 3
11=divide by 4
3
GPIOPOL
GPIOSEL
0
GPIO Polarity invert
0=Non inverted
1=Inverted
General Purpose
Input Output
2:0
000
GPIO function select:
000=GPIO off
General Purpose
Input Output
001= Jack insert detect
010=Temp ok
011=Amute active
100=PLL clk o/p
101=PLL lock
110=Reserved
111=Reserved
PP, Rev 3.3, December 2007
80
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
