Pre Production
WM8941
REGISTER
ADDRESS
BIT
3:0
LABEL
PLLN[3:0]
DEFAULT
DESCRIPTION
REFER TO
1100
Integer (N) part of PLL input/output frequency ratio.
Use values greater than 5 and less than 13.
Master Clock and
Phase Locked
Loop (PLL)
37 (25h)
38 (26h)
39 (27h)
40 (28h)
15:6
5:0
000h
Reserved
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
001100
Fractional (K) part of PLL1 input/output frequency ratio Master Clock and
(treat as one 24-digit binary number).
Reserved
Phase Locked
Loop (PLL)
15:9
8:0
00h
010010011 Fractional (K) part of PLL1 input/output frequency ratio Master Clock and
(treat as one 24-digit binary number).
Reserved
Phase Locked
Loop (PLL)
15:9
8:0
00h
011101001 Fractional (K) part of PLL1 input/output frequency ratio Master Clock and
(treat as one 24-digit binary number).
Phase Locked
Loop (PLL)
15:5
4
000h
Reserved
QBOOST
VBGAIN
0
0
Increases the filters Q.
Video buffer gain
Video Buffer
Video Buffer
3
0 = 0dB (=6dB unloaded)
1 = +6dB (=12dB unloaded)
Disable Video Buffer DC Offset
0 = Video buffer drives down to 40mV above ground
1 = Video buffer drives to ground (not recommended)
Video buffer pull down
Video buffer clamp enable
0 = Disabled
2
VBDISOFF
0
Video Buffer
1
0
VBPULLDWN
VBCLAMPEN
0
0
Video Buffer
Video Buffer
1 = Enabled
41 (29h)
42 (2Ah)
15:0
15:2
1
0000h
0
Reserved
Reserved
ALC Control 4
ALCZC
0 (zero
cross off)
ALC uses zero cross detection circuit.
0 = Disabled (recommended)
1 = Enabled
0
0
Reserved
43 (2Bh)
44 (2Ch)
15:0
15:9
8
0000h
00h
0
Reserved
Reserved
MBVSEL
Microphone Bias Voltage Control
0 = 0.9 * AVDD
Input Signal Path
1 = 0.75 * AVDD
7:4
3
0h
0
Reserved
AUXMODE
Auxiliary Input Mode
0 = inverting buffer
Input Signal Path
Input Signal Path
1 = mixer (on-chip input resistor bypassed)
2
1
AUX2INPPGA
0
1
Select AUX amplifier output as input PGA signal
source.
0=AUX not connected to input PGA
1=AUX connected to input PGA amplifier negative
terminal.
MICN2INPPGA
Connect MICN to input PGA negative terminal.
0=MICN not connected to input PGA
Input Signal Path
1=MICN connected to input PGA amplifier negative
terminal.
PP, Rev 3.3, December 2007
85
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
