Pre Production
WM8941
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
1
0
ALRSWAP
0
Controls whether ADC data appears in ‘right’ or ‘left’
phases of FRAME clock:
Digital Audio
Interfaces
0=ADC data appear in ‘left’ phase of FRAME
1=ADC data appears in ‘right’ phase of FRAME
Reserved
0
5 (05h)
15:7
6
00h
0
Reserved
DAC_LOOPBA
CK
Digital loopback function
0=No DAC loopback
Digital Audio
Interfaces
1=Loopback enabled, DAC data input is fed directly
into ADC data output.
5
WL8
0
8 Bit Word Length for companding
0=Word Length controlled by WL
1=8 bits
Digital Audio
Interfaces
4:3
DAC_COMP
00
DAC companding
00=off
Digital Audio
Interfaces
01=reserved
10=µ-law
11=A-law
2:1
ADC_COMP
00
ADC companding
00=off
Digital Audio
Interfaces
01=reserved
10=µ-law
11=A-law
0
ADC_LOOPBA
CK
0
Digital loopback function
0=No ADC loopback
Digital Audio
Interfaces
1=Loopback enabled, ADC data output is fed directly
into DAC data input.
6 (06h)
15:9
8
00h
1
Reserved
CLKSEL
Controls the source of the clock for all internal
operation:
Digital Audio
Interfaces
0=MCLK
1=PLL output
7:5
4:2
1
MCLKDIV
010
000
0
Sets the scaling for either the MCLK or PLL clock
output (under control of CLKSEL)
Digital Audio
Interfaces
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
BCLKDIV
Configures the BCLK and FRAME output frequency,
for use when the chip is master over BCLK.
Digital Audio
Interfaces
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Reserved
PP, Rev 3.3, December 2007
79
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
