Pre Production
WM8941
If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low
power operation.
INPUT CLOCK
(F1)
DESIRED PLL
OUTPUT (F2)
DIVISION
FRACTIONAL
INTEGER
SDM
REQUIRED (R) DIVISION (K) DIVISION (N)
11.2896MHz
12.2880MHz
90.3168MHz
98.3040MHz
8
8
0
0
8
8
0
0
Table 49 PLL Modes of Operation (Integer N mode)
FRACTIONAL K MODE
The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up
to 1/224). If these are used then FRAC_EN must be set. The relationship between the required
division X, the fractional division K[23:0] and the integer division N[3:0] is:
K = 224 ( R – N)
where 0 < (R – N) < 1 and K is rounded to the nearest whole number.
EXAMPLE:
PLL input clock (f1) is 12MHz and the required clock (SYSCLK) is 12.288MHz.
R should be chosen to ensure 5 < N < 13. There is a fixed divide by 4 in the PLL and a selectable
divider (MCLKDIV[3:0]) after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f2 = 4 * 2 * 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
N = int R = 8
K = int (224 x (8.192 – 8)) = 3221225 = 3126E9h
So N[3:0] will be 8h and K[23:0] will be 3126E9h to produce the desired 98.304MHz clock.
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in Table 56.
MCLK
DESIRED
OUTPUT
(MHz)
F2
PRESCALE POSTSCALE
R
N
K
(MHz)
(MHz)
DIVIDE
DIVIDE
(Hex)
(Hex)
(MCLKDIV)
12
12
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
7.5264
8.192
7
8
6
7
6
6
9
A
9
9
9
9
7
8
6
7
6
7
86C226
3126E9
F28BD4
8FD525
45A1CA
D3A06E
6872B0
3D70A3
2DB492
FD809F
1F76F8
EE009E
86C226
3126E9
F28BD4
8FD525
BOAC93
482296
13
6.947446
7.561846
6.272
13
14.4
14.4
19.2
19.2
19.68
19.68
19.8
19.8
24
6.826667
9.408
10.24
9.178537
9.990243
9.122909
9.929697
7.5264
24
8.192
26
6.947446
7.561846
6.690133
7.281778
26
27
27
Table 50 PLL Frequency Examples
PP, Rev 3.3, December 2007
65
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
