Pre Production
WM8941
REGISTER
ADDRESS
BIT
3:1
LABEL
DEFAULT
000
DESCRIPTION
R7
SR
Approximate sample rate (configures the
coefficients for the internal digital filters):
Additional
control
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
Table 46 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8941 has an on-chip phase-locked loop (PLL) circuit that can be used to:
•
•
Generate master clocks for the WM8940 audio functions from another external clock, e.g.
in telecoms applications.
Generate an output clock, on GPIO, for another part of the system (derived from an
existing audio master clock).
Table 47 shows the PLL and internal clocking arrangement on the WM8941.
The PLL is enabled or disabled by the PLLEN register bit.
Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are
set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1
5
PLLEN
0
PLL enable
0=PLL off
1=PLL on
Power
Management 1
Table 47 PLLEN Control Bit
PP, Rev 3.3, December 2007
63
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
