WM8940
Pre-Production
1/fs
1 BCLK
1 BCLK
LRC
falling edge can occur anywhere in this area
BCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT /
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
Input Word Length (WL)
Figure 29 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1)
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below.
Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK,
and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with
BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses
at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.
REGISTER
ADDRESS
BIT
LABEL
LOUTR
DEFAULT
DESCRIPTION
LOUTR control
R4
9
0
Audio interface
control
0=normal
1=Input mono channel data output on
both left and right channels
8
7
BCP
0
0
BCLK polarity
0=normal
1=inverted
FRAMEP
Frame clock polarity (for RJ, LJ and I2S
formats)
0=normal
1=inverted
DSP Mode control
1 = Configures interface so that MSB is
available on 1st BCLK rising edge after
FRAME rising edge
0 = Configures interface so that MSB is
available on 2nd BCLK rising edge after
FRAME rising edge
6:5
4:3
WL
10
10
Word length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits (see note)
Audio interface Data Format Select:
00=Right Justified
01=Left Justified
10=I2S format
FMT
11= DSP/PCM mode
Pre-Production, Rev 3.0, February 2007
52
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
