Pre-Production
WM8940
Figure 30 PLL and Clock Select Circuit
The PLL frequency ratio R = f2/f1 (see Figure 30) can be set using the register bits PLLK and PLLN.
N controls the ratio of the division, and K the fractional part.
The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz.
The PLL output then passes through a fixed divide by 4, and can also be further divided by
MCLKDIV[3:0] (see figure 34). The divided clock (SYSCLK) can be used to clock the WM8940
DSP.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
PLL POWER
R36
7
PLL_POWERDOWN
0
0=ON
PLL N value
1=OFF
6
FRACEN
1
Fractional Divide within the PLL
0=Disabled (Lower Power)
1=Enabled
5:4 PLLPRESCALE
00
00 = MCLK input multiplied by 2
(default)
01 = MCLK input not divided (default)
10 = Divide MCLK by 2 before input to
PLL
11 = Divide MCLK by 4 before input to
PLL
3:0 PLLN
1100
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
R37
5:0 PLLK [23:18]
8:0 PLLK [17:9]
8:0 PLLK [8:0]
0Ch
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
PLL K value 1
R38
093h
0E9h
PLL K Value 2
R39
PLL K Value 3
Table 47 PLL Frequency Ratio Control
Pre-Production, Rev 3.0, February 2007
55
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
