WM8940
Pre-Production
INTEGER N DIVISION
The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12.
If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low
power operation.
INPUT CLOCK
DESIRED PLL OUTPUT
(PLL_OUT)
DIVISION
REQUIRED (X)
FRACTIONAL
DIVISION (K)
INTEGER
DIVISION (N)
SDM
(PLL_IN)
11.2896MHz
12.288MHz
90.3168MHz
98.304MHz
8
8
0
0
8
8
0
0
Table 48 PLL Modes of Operation (Integer N mode)
FRACTIONAL K MODE
The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up
to 1/224). If these are used then FRAC_EN must be set. The relationship between the required
division X, the fractional division K[23:0] and the integer division N[3:0] is:
K = 223 ( X – N)
where 0 < (X – N) < 1 and K is rounded to the nearest whole number.
For example, if the PLL input clock (PLL_IN) is 13MHz and the desired PLL output clock (PLLCLK)
is 98.304MHz then the desired division, X, is 7.561800. So N[3:0] will be 7h and K[23:0] will be
23F400h to produce the desired 98.304MHz clock.
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in Table 49.
MCLK
(MHz)
(F1)
12
DESIRED
OUTPUT
(MHz)
F2
PRESCALE POSTSCALE
R
N
K
(MHz)
DIVIDE
DIVIDE
(Hex)
(Hex)
(FIXED)
11.29
12.288
11.29
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
7.5264
8.192
7
8
6
7
6
6
9
A
9
9
9
9
7
8
6
7
6
7
86C220
3126E8
F28BD4
8FD525
45A1CA
D3A06E
6872AF
3D70A3
2DB492
FD809F
1F76F7
EE009E
86C226
3126E8
F28BD4
8FD525
BOAC93
482296
12
13
6.947446
7.561846
6.272
13
12.288
11.29
14.4
14.4
19.2
19.2
19.68
19.68
19.8
19.8
24
12.288
11.29
6.826667
9.408
12.288
11.29
10.24
9.178537
9.990243
9.122909
9.929697
7.5264
12.288
11.29
12.288
11.29
24
12.288
11.29
8.192
26
6.947446
7.561846
6.690133
7.281778
26
12.288
11.29
27
27
12.288
Table 49 PLL Frequency Examples
Pre-Production, Rev 3.0, February 2007
56
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
