WM8940
Pre-Production
DIGITAL AUDIO INTERFACES
The audio interface has four pins:
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ADCDAT: ADC data output
DACDAT: DAC data input
FRAME: Data alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK, and FRAME can be outputs when the WM8940 operates as a master, or
inputs when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
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•
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Left justified
Right justified
I2S
DSP mode A / B
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8940 audio interface may be configured as either master or slave. As a master interface
device the WM8940 generates BCLK and FRAME and thus controls sequencing of the data transfer
on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In
slave mode (MS=0), the WM8940 responds with data to clocks it receives over the digital audio
interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.
Figure 25 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.
Pre-Production, Rev 3.0, February 2007
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
