Production Data
WM8912
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
1XX = 16
000 recommended for high FREF
011 recommended for low FREF
Register 75h FLL Control 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R118 (76h)
FLL Control
3
15:0
FLL_K [15:0] 0000_0000 Fractional multiply for FREF
_0000_000
0
(MSB = 0.5)
Register 76h FLL Control 3
REGISTER
ADDRESS
BIT
14:5
3:0
LABEL
DEFAULT
DESCRIPTION
REFER TO
R119 (77h)
FLL Control
4
FLL_N [9:0]
01_0111_0 Integer multiply for FREF
111
(LSB = 1)
FLL_GAIN [3:0]
0000
FLL Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not changed from
default.
Register 77h FLL Control 4
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R120 (78h)
FLL Control
5
4:3
FLL_CLK_REF
_DIV [1:0]
00
FLL Clock Reference Divider
00 = MCLK / 1
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK (or other input reference) must be divided down
to <=13.5MHz.
For lower power operation, the reference clock can be
divided down further if desired.
1:0
FLL_CLK_REF
_SRC [1:0]
00
FLL Clock source
00 = MCLK
01 = BCLK
10 = LRCLK
11 = Reserved
Register 78h FLL Control 5
PD, Rev 4.0, September 2010
117
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
