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WM8912GEFL/RV 参数 Datasheet PDF下载

WM8912GEFL/RV图片预览
型号: WM8912GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗DAC与耳机驱动器的便携式音频应用 [Ultra Low Power DAC with Headphone Driver for Portable Audio Applications]
分类和应用: 驱动器便携式
文件页数/大小: 128 页 / 1259 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8912  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Removes LINEOUTL short  
REFER TO  
R94 (5Eh)  
Analogue  
Lineout 0  
7
LINEOUTL_RM  
V_SHORT  
0
0 = LINEOUTL short enabled  
1 = LINEOUTL short removed  
For normal operation, this bit should be set as the final  
step of the LINEOUTL Enable sequence.  
6
5
LINEOUTL_EN  
A_OUTP  
0
0
Enables LINEOUTL output stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the DC offset cancellation has been scheduled.  
LINEOUTL_EN  
A_DLY  
Enables LINEOUTL intermediate stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the output signal path has been configured, and before  
DC offset cancellation is scheduled. This bit should be  
set with at least 20us delay after LINEOUTL_ENA.  
4
3
2
1
LINEOUTL_EN  
A
0
0
0
0
Enables LINEOUTL input stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set as the first  
step of the LINEOUTL Enable sequence.  
LINEOUTR_R  
MV_SHORT  
Removes LINEOUTR short  
0 = LINEOUTR short enabled  
1 = LINEOUTR short removed  
For normal operation, this bit should be set as the final  
step of the LINEOUTR Enable sequence.  
LINEOUTR_EN  
A_OUTP  
Enables LINEOUTR output stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the DC offset cancellation has been scheduled.  
LINEOUTR_EN  
A_DLY  
Enables LINEOUTR intermediate stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the output signal path has been configured, and before  
DC offset cancellation is scheduled. This bit should be  
set with at least 20us delay after LINEOUTR_ENA.  
0
LINEOUTR_EN  
A
0
Enables LINEOUTR input stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set as the first  
step of the LINEOUTR Enable sequence.  
Register 5Eh Analogue Lineout 0  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
REFER TO  
R98 (62h)  
Charge  
Pump 0  
0
CP_ENA  
0
Enable charge-pump digits  
0 = disable  
1 = enable  
Register 62h Charge Pump 0  
PD, Rev 4.0, September 2010  
113  
w
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