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WM8912GEFL/RV 参数 Datasheet PDF下载

WM8912GEFL/RV图片预览
型号: WM8912GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗DAC与耳机驱动器的便携式音频应用 [Ultra Low Power DAC with Headphone Driver for Portable Audio Applications]
分类和应用: 驱动器便携式
文件页数/大小: 128 页 / 1259 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8912  
Production Data  
REFER TO  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Removes HPOUTL short  
R90 (5Ah)  
Analogue  
HP 0  
7
HPL_RMV_SH  
ORT  
0
0 = HPOUTL short enabled  
1 = HPOUTL short removed  
For normal operation, this bit should be set as the final  
step of the HPL Enable sequence.  
6
5
HPL_ENA_OU  
TP  
0
0
Enables HPOUTL output stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the DC offset cancellation has been scheduled.  
HPL_ENA_DL  
Y
Enables HPOUTL intermediate stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the output signal path has been configured, and before  
DC offset cancellation is scheduled. This bit should be  
set with at least 20us delay after HPL_ENA.  
4
3
2
1
HPL_ENA  
0
0
0
0
Enables HPOUTL input stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set as the first  
step of the HPL Enable sequence.  
HPR_RMV_SH  
ORT  
Removes HPOUTR short  
0 = HPOUTR short enabled  
1 = HPOUTR short removed  
For normal operation, this bit should be set as the final  
step of the HPR Enable sequence.  
HPR_ENA_OU  
TP  
Enables HPOUTR output stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the DC offset cancellation has been scheduled.  
HPR_ENA_DL  
Y
Enables HPOUTR intermediate stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set to 1 after  
the output signal path has been configured, and before  
DC offset cancellation is scheduled. This bit should be  
set with at least 20us delay after HPR_ENA.  
0
HPR_ENA  
0
Enables HPOUTR input stage  
0 = Disabled  
1 = Enabled  
For normal operation, this bit should be set as the first  
step of the HPR Enable sequence.  
Register 5Ah Analogue HP 0  
PD, Rev 4.0, September 2010  
112  
w
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